The present invention relates to semiconductor devices and, more particularly, to a method of manufacturing a semiconductor device, in which an overlay vernier is formed.
In general, when fabricating semiconductor devices, a patterning process for forming a pattern on a semiconductor substrate is performed. In order to perform the patterning process, a photoresist is formed on the semiconductor substrate and then an exposure process for photosensitizing the photoresist by irradiating light on a photomask photo or a reticle is performed.
A development process for removing the patterns of the photoresist that has been photosensitized by the exposure process is performed. After the development process, an overlay vernier formed through the above processes is measured by irradiating light.
The overlay vernier is formed in order to know and correct an alignment state between a layer formed in a previous process (when fabricating a semiconductor device of a stack structure) and a layer formed in a current process. The overlay vernier is formed on the semiconductor substrate along with a real pattern, preferably by forming a step.
In other words, a lower overlay vernier pattern is formed along with the formation of a lower layer pattern of a real cell, and an upper overlay vernier pattern is formed along with the formation of an upper layer pattern of the real cell. The degree in which the two layers overlap with each other is detected by using the lower overlay vernier pattern and the upper overlay vernier pattern.
Meanwhile, in order to perform the exposure process, an alignment process by reading an alignment key using irradiating light must be performed. Accordingly, the alignment process can be performed only when a step, which becomes a visible marker for reading using light, is formed or an upper hard mask is made from transparent material. Furthermore, the measurement of the overlay vernier, which is performed after the development process, also can only be performed when a step is formed or an upper hard mask is made from transparent material.
As the size of a semiconductor device is gradually miniaturized and the level of integration of a semiconductor device is gradually increased, however, a technique for forming a micro pattern has been developed. In the past, the hard mask was formed from oxide, etc. through which light can pass. However, recently, the hard mask has been formed from amorphous carbon.
Amorphous carbon is an opaque material through which light cannot pass. Thus, in order to perform an alignment process performed at the time of the exposure process and an overlay vernier read process performed after the development process, an additional process for forming a step must be carried out.
Therefore, after a drain key open mask process and a drain key open etch process are performed after the deposition of an insulating layer, an amorphous carbon hard mask or the like, must be formed on the upper side. However, it increases the process steps compared to using the transparent hard mask. Consequently, there are problems in that an overall process time is lengthened and the cost of production is increased.